Journal of Advanced Engineering Technology and Management
ISSN (Online): 3049-3684
Volume: 1 Issue: 1 | Open Access | 10 Dec 2025
Compiler Optimization Techniques for Energy-Efficient High-Performance Computing Systems
Kalsa Trivedi, Engineering Student, Final Year, LPU
Abstract: Energy is now a first-order constraint for High-Performance Computing (HPC). While hardware advances (DVFS, energy-proportional servers, accelerators) are important, compilers can substantially reduce energy-to-solution by reducing instruction counts, improving data locality, enabling efficient use of vector/SIMD units, and coordinating with runtime power management. This paper surveys compiler techniques for energy-efficient HPC—loop transformations (tiling, temporal blocking), data-layout and locality optimizations, vectorization and scheduling, register allocation and spill reduction, polyhedral compilation, profile-guided auto-tuning, and compiler-directed DVFS/power hints—and presents an LLVM-centric prototype flow, energy modeling approaches, representative experimental findings from literature, and open research directions. Our synthesis highlights practical tradeoffs and shows that integrated compiler + runtime approaches can achieve substantial energy savings with acceptable performance tradeoffs.
Keywords: Compiler optimizations, energy efficiency, DVFS, polyhedral compilation, LLVM, loop tiling, temporal blocking, HPC.
References
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